The present invention generally pertains to semiconductor circuits, and is particularly directed to an improved TTL to CMOS input buffer circuit.
A typical input buffer for a CMOS circuit essentially includes a CMOS inverter, as shown in FIG. 1. The CMOS inverter includes a p-channel field effect transistor (FET) P connected to a supply terminal Vcc and a n-channel FET connected to a ground terminal. The gate of each FET, is connected to an input terminal V.sub.IN which in turn may be connected to an output terminal of a TTL device. The drains of the two FET's are connected together at an output terminal V.sub.OUT.
The ideal output transfer characteristic for the typical input buffer circuit of FIG. 1 is shown in FIG. 2, wherein the trip point for the buffer circuit is shown as occurring at one-half the supply voltage, 1/2 Vcc. However, this transfer characteristic is but an ideal; and in reality, the trip point is affected by variations in the process by which the CMOS inverter is fabricated.
FIG. 3 illustrates the span of trip point variation in the output transfer characteristic that is due to variations in the fabrication process. These process variations affect the gain of the p-channel FET and the n-channel FET so that the gain for each type of device is within a range between a specified maximum gain and a specified minimum gain related to the tolerances specified for the fabrication process. A CMOS FET having a high gain has a relatively low threshold voltage for being gated on and rendered conductive, whereas, a CMOS FET having a low gain has a relatively high threshold voltage for being gated on and rendered conductive. When the CMOS inverter of FIG. 1 includes a p-channel FET having the specified maximum gain and a n-channel FET having the specified minimum gain, the trip point is at V.sub.T MAX, as shown in FIG. 3. When the inverter of FIG. 1 includes a p-channel FET having the minimum specified gain and a n-channel FET having a maximum specified gain, the trip point is at V.sub.T MIN. The span of trip point variation, .DELTA.V.sub.T = V.sub.T MAX - V.sub.T MIN.
The span of trip point variation also is affected by such factors as the supply voltage Vcc and temperature. However, such variations are minor in comparison to variations due to the fabrication process.
For a fixed supply voltage and temperature the span of trip point variation .DELTA. V.sub.T typically is within a range of from 1.5 volts to 1.8 volts. However, in order for the CMOS inverter to function as an input buffer circuit to a CMOS device from a TTL device, the span of trip point variation cannot exceed 1.2 volts and still be compatible with the TTL device.
In accordance with the prior art, in order to achieve compatibility with the TTL device, either external components must be inserted between the output of the TTL device and the CMOS input buffer circuit, or the CMOS input buffer circuit must be fabricated according to tighter process tolerances so as to reduce the specified range between the maximum and minimum gains for the n-channel FET's and p-channel FET's. Both alternatives are unattractive from the standpoint of cost.